1. Field of Invention
The present invention relates to a source driving circuit in an electronic device with enhanced driving capability.
2. Description of Related Art
In a liquid crystal display, a source driver applies analog voltages to the display panel. The source driver should have high-speed operation, accuracy and less power consumption.
The source driver receives video data from a timing controller, converts the video data into a high-voltage analog signal suitable for the panel, and outputs the high voltage analog signal to the panel on a horizontal line basis.
For displaying a high-quality image, the color depth and resolution of the panel increases, which in turn imposes a rigorous timing to process more bits of data during a given cycle.
FIG. 1a is a block diagram of a display device including a source driver and a display panel 19. The source driver includes a plurality of channels 10-1, 10-2 . . . 10-i. Each of the channels 10-1, 10-2 . . . 10-i includes a latch 12, a digital-to-analog converter (DAC) 14, and a buffer 16.
FIG. 1b is a timing diagram illustrating an operation of the source driving circuit illustrated in FIG. 1a. Referring to FIG. 1b, in response to a horizontal synchronization signal Hsync that is an input signal of the timing controller, RGB video data ( . . . , N−1, N, N+1, N+2, N+3, . . . ) are sequentially input into the channels 10-1, 10-2, . . . , 10-i. The input data ( . . . , N−1, N, N+1, N+2, N+3, . . . ) are sequentially or simultaneously converted into analog signals at the channels 10-1, 10-2, . . . , 10-i, and the analog signals are simultaneously output to the display panel 20 through the output switches SW of the channels 10-1, 10-2, . . . , 10-i. 
In an example, data N−1 corresponding to a first horizontal line are sequentially input into the channels 10-1, 10-2, . . . , 10-i during a period I. The input data N−1 are converted into analog signals by the channels 10-1, 10-2, . . . , 10-i. The analog signals are simultaneously output to the display panel 19 through the output switches of the channels 10-1, 10-2, . . . , 10-i during a second period II.
Similarly, the data N corresponding to a second horizontal line are sequentially input into the channels 10-1, 10-2, . . . , 10-i during the period II. The input data N are converted into analog signals by the channels 10-1, 10-2, . . . , 10-i, and the analog signals are simultaneously output to the display panel 19 through the output switches of the channels 10-1, 10-2, . . . , 10-i during a third period III.
There are plural logic gates in the circuits of the channels 10-1, 10-2, . . . , 10-i, such as CMOS inverters. The rise time and fall time of logic gates should be designed as short as possible. The rise time and fall time of inverters, for example, are related to power supply, W/L ratio of transistors, and output loading. In one example, the output driving ability of inverters degrades rapidly when the power supply voltage is lower than a normal voltage. This is because the turn-on current of PMOS transistors is proportional to square of (VSG-Vth), VSG refers to source-gate voltage of PMOS transistors and Vth refers to threshold voltage of PMOS transistor. Thus, the driving ability of PMOS transistors and CMOS inverters degrade due to the lower turn-on current.
Typically, design of power supply is related to CMOS process. For example, power supply of 3.3V is used in 0.35 μm process devices; power supply of 5V is used in 0.5 μm process devices. However, in some cases, the requirement is to implement power supply of 1.8V in 0.5 μm process devices or power supply of 1.3V in 0.35 μm process devices. The issue of degradation of driving ability due to low power supply voltage gets more and more serious. Further, when driving a heavy loading, the rise time and fall time also degrade.
Therefore, there is a need to design a circuit with enhanced driving capability, even in case of low power supply voltage and low end process.